The present invention concerns a semiconductor device and a method of manufacturing the semiconductor device.
Along with refinement of interconnects in semiconductor devices in recent years, various structures of semiconductor devices have been proposed.
Japanese Unexamined Patent Application Publication No. 2010-141230 describes the following semiconductor device. A first interconnect and a gate electrode are provided in an insulating layer of a first interconnect layer. A gate insulating film is provided in contact with the gate electrode over the first interconnect layer. A semiconductor layer is provided over the gate insulating film. The semiconductor device comprises the gate electrode, the gate insulating film, and the semiconductor layer. Thus, an element having a new function can be formed in the interconnect layer.
WO 2007/063966 describes the following semiconductor device using an oxide semiconductor. An n-type oxide semiconductor layer is provided over a substrate. In the n-type oxide semiconductor layer, an oxide conductor layer is provided over both sides of a channel portion. A gate insulating film is provided over the n-type oxide semiconductor layer and the oxide conductor layer. A gate electrode is provided over the gate insulating film. It is described that this can improve the production yield.
Japanese Unexamined Patent Application Publication No. 2007-157932 describes the following semiconductor device. An integrated circuit is formed over a semiconductor substrate. An insulation having a concave portion is provided over the integrated layer circuit. An amorphous semiconductor layer (substantially single crystal semiconductor particle) is formed so as to cover the insulating layer and the concave portion. In the amorphous semiconductor layer, a source region and a drain region are formed at positions isolated from each other by ion implantation. A gate insulating film is provided over the amorphous semiconductor layer. Over the gate insulating film, a gate electrode is provided in a region positioned between the source region and the drain region in a plan view. The source electrode and the drain electrode are provided in an interconnect layer above the amorphous semiconductor layer. That is, the source electrode and the drain electrode are in contact with the amorphous semiconductor layer on the side identical with the gate electrode. It is described that increase in the chip area can be suppressed. It is further disclosed that the amorphous semiconductor layer or substantially single crystal semiconductor particle comprises Si. This document does not disclose a case where the amorphous semiconductor layer comprises other materials.
A semiconductor device having an amorphous InGaZnO4 film sputtered at a low temperature is disclosed in “High-mobility thin-film transistor with amorphous InGaZnO4 channel fabricated by room temperature rf-magnetron sputtering”, Hisao Yabuta, et al. in App. Phys. Lett., Vol. 89, 112123 (2006)).